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256mb: x32 mobile sdram features pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_1.fm - rev. g 6/05 1 ?2003 micron technology, inc. all rights reserved. products and specifications discus sed herein are subject to chan ge by micron without notice. mobile sdram mt48lc8m32lf, mt48v8m32lf, mt48 h8m32lf - 2 meg x 32 x 4 banks for the latest data sheet, refer to micron?s web site: www.micron.com/produ cts/dram/mobile features ?low voltage power supply ? partial array self refresh power-saving mode ? temperature compensated self refresh (tcsr) ? deep power-down mode ? programmable output drive strength ? fully synchronous; all signals registered on positive edge of system clock ? internal pipelined operation; column address can be changed every clock cycle ? internal banks for hiding row access/precharge ? programmable burst lengths: 1, 2, 4, 8, or full page ? auto precharge, includes concurrent auto precharge, and auto refresh modes ? self-refresh mode; standard and low power ? 64ms, 4,096-cycle refresh ? lvttl-compatible inputs and outputs ? commercial and industri al temperature ranges ? supports cas latency of 1, 2, 3 table 1: addressing 8 meg x 32 configuration 2 meg x 32 x 4 banks refresh count 4k row addressing 4k (a0?a11) bank addressing 4 (ba0, ba1) column addressing 512 (a0?a8) options marking ?v dd /v dd q ? 3.3v/3.3v lc ? 2.5v/2.5v v ? 1.8v/1.8v h ? configurations ? 8 meg x 32 (2 meg x 32 x 4 banks) 8m32 ? package/ballout ? 90-ball vfbga (8mm x 13mm) (standard) f5 ? 90-ball vfbga (8mm x 13mm) (lead-free) b5 ? timing (cycle time) ? 7.5ns @ cl = 3 (133 mhz) -75 ? 7.5ns @ cl = 2 (104 mhz) -75 ? 8ns @ cl = 3 (125 mhz) -8 ? 8ns @ cl = 2 (104 mhz) -8 ? 10ns @ cl = 3 (100 mhz) -10 ? 10ns @ cl = 2 (83 mhz) -10 ? operating temperature range ? commercial (0 to +70c) none ? industrial (-40c to +85c) it table 2: key timing parameters cl = cas (read) latency speed grade clock frequency access time setup time hold time cl = 2 cl = 3 -75 133 mhz ? 6ns 2.5ns 1ns -8 125 mhz ? 7ns 2.5ns 1ns -10 100 mhz ? 7ns 2.5ns 1ns -75 133 mhz 7ns ? 2.5ns 1ns -8 104 mhz 8ns ? 2.5ns 1ns -10 83 mhz 8ns - 2.5ns 1ns
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32toc.fm - rev. g 6/05 2 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 fbga part number system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 ball assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 bank/row activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32lof.fm - rev. g 6/05 3 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram list of figures list of figures figure 1: functional block diagram 8 meg x 32 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 2: 90-ball vfbga (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 3: mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 4: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 5: low power extended mode register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 6: activating a specific row in a specific bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 7: example: meeting trcd (min) when 2 < trcd (min)/tck < 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 8: read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 9: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 10: consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 11: random read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 12: read to write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 13: read to write with extra clock cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 14: read to precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 15: terminating a read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 16: write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 17: write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 18: write to write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 19: random write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 20: write to read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 21: write to precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 22: terminating a write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 23: precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 24: power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 25: clock suspend during write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 26: clock suspend during read burs t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 27: read with auto precharge interrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 28: read with auto precharge interrupted by a write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 29: write with auto precharge interrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 30: write with auto precharge interrupted by a write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 31: typical self refresh current vs. temperature ? 3.3v part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 32: typical self refresh current vs. temperature ? 2.5v part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 33: typical self refresh current vs. temperature ? 1.8v part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 34: initialize and load mode register 1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 35: power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 36: clock suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 37: auto refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 38: self refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 39: read ? without auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 40: read ? with auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 41: single read ? without auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 figure 42: single read ? with auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 figure 43: alternating bank read accesses 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 figure 44: read ? full-page burst 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 figure 45: read ? dqm operation 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 figure 46: write ? wi thout auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 47: write ? wi th auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 48: single write ? without auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 figure 49: single write ? with auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 figure 50: alternating bank write accesses 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 figure 51: write ? full-page burst 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 figure 52: write ? dqm operation 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 figure 53: 90-ball vfbga (8mm x 13mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32lot.fm - rev. g 6/05 4 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram list of tables list of tables table 1: addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: key timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 3: cross reference for vfbga device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 table 4: ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 5: burst definition table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 6: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 7: truth table ? commands and dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 8: truth table ? cke. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 9: truth table ? current state bank n , command to bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 10: truth table ? current state bank n , command to bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 11: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 12: dc electrical characteristics and operating conditions (lc version) . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 13: dc electrical characteristics and operating conditions (v version) . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 14: dc electrical characteristics and operating conditions (h version) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 15: electrical characteristics and re commended ac operating conditions . . . . . . . . . . . . . . . . . . . . . . .48 table 16: ac functional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 17: i dd specifications and conditions (lc version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 18: i dd specifications and conditions (v version). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 19: i dd specifications and conditions (h version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 20: i dd 7 ? self refresh current options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 21: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 5 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram fbga part number system fbga part number system due to space limitations, fbga-packaged co mponents have an abbreviated part mark- ing that is different from the part number. for a quick conversion of an fbga code, see the fbga part marking decoder on micron?s web site, www.micron.com/decoder . general description the micron ? 256mb sdram is a high-speed cmos, dynamic random-access memory containing 268,435,456 bits. it is internally configured as a quad-bank dram with a syn- chronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the 67,108,864-bit banks is organized as 4,096 rows by 512 columns by 32 bits. read and write accesses to the sdram are bu rst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registrati on of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0?a11 select the row). the address bits registered coincident with the read or write command are used to select the st arting column location for the burst access. the sdram provides for programmable read or write burst lengths of 1, 2, 4, or 8 loca- tions, or the full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. the 256mb sdram uses an internal pipelined architecture to achieve high-speed oper- ation. this architecture is compatible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high- table 3: cross reference for vfbga device marking part number v dd /v dd q architecture vfbga production marking mt48lc8m32lff5-75 3.3v/3.3v 8 meg x 32 90-ball, 8 x 13mm d9fmq mt48lc8m32lff5-8 3.3v/3.3v 8 meg x 32 90-ball, 8 x 13mm d9cch mt48lc8m32lff5-10 3.3v/3.3v 8 meg x 32 90-ball, 8 x 13mm d9cck mt48lc8m32lfb5-75 3.3v/3.3v 8 meg x 32 90-ball, 8 x 13mm d9fmx mt48lc8m32lfb5-8 3.3v/3.3v 8 meg x 32 90-ball, 8 x 13mm d9ccw mt48lc8m32lfb5-10 3.3v/3.3v 8 meg x 32 90-ball, 8 x 13mm d9ccz mt48v8m32lff5-75 2.5v/2.5v 8 meg x 32 90-ball, 8 x 13mm d9fms mt48v8m32lff5-8 2.5v/2.5v 8 meg x 32 90-ball, 8 x 13mm d9ccm mt48v8m32lff5-10 2.5v/2.5v 8 meg x 32 90-ball, 8 x 13mm d9ccp mt48v8m32lfb5-75 2.5v/2.5v 8 meg x 32 90-ball, 8 x 13mm d9fmz mt48v8m32lfb5-8 2.5v/2.5v 8 meg x 32 90-ball, 8 x 13mm d9cdc mt48v8m32lfb5-10 2.5v/2.5v 8 meg x 32 90-ball, 8 x 13mm d9cdf mt48h8m32lff5-75 1.8v/1.8v 8 meg x 32 90-ball, 8 x 13mm d9fmv mt48h8m32lff5-8 1.8v/1.8v 8 meg x 32 90-ball, 8 x 13mm d9ccr mt48h8m32lff5-10 1.8v/1.8v 8 meg x 32 90-ball, 8 x 13mm d9cct mt48h8m32lfb5-75 1.8v/1.8v 8 meg x 32 90-ball, 8 x 13mm d9fnb mt48h8m32lfb5-8 1.8v/1.8v 8 meg x 32 90-ball, 8 x 13mm d9cdj MT48H8M32LFB5-10 1.8v/1.8v 8 meg x 32 90-ball, 8 x 13mm d9cdl
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 6 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram general description speed, fully random access. precharging one bank while accessing on e of the other three banks will hide the precharge cycles and provide seamless high-speed, random-access operation. the 256mb sdram is designed to operate in 3.3v, 2.5v, and 1.8v low-power memory systems. an auto refresh mode is provided, along with a power-saving, deep power- down mode. all inputs and ou tputs are lvttl-compatible. sdrams offer substantial advances in dr am operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to inte rleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle dur- ing a burst access. figure 1: functional bl ock diagram 8 meg x 32 sdram 12 ras# cas# row- address mux clk cs# we# cke control logic column- address counter/ latch mode register 9 command decode a0-a11, ba0, ba1 dqm0, dqm3 12 address register 14 512 (x32) 4096 i/o gating dqm mask logic read data latch write drivers column decoder bank0 memory array (4,096 x 512 x 32) bank0 row- address latch & decoder 4096 sense amplifiers bank control logic dq0- dq31 32 32 data input register data output register 32 12 bank1 bank2 bank3 12 9 2 4 4 2 refresh counter ba1 ba0 bank 000 011 102 113
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 7 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram ball assignment ball assignment figure 2: 90-bal l vfbga (top view) 1234 6789 5 dq26 dq28 v ss q v ss q v dd q v ss a4 a7 clk dqm1 v dd q v ss q v ss q dq11 dq13 dq24 v dd q dq27 dq29 dq31 dqm3 a5 a8 cke nc dq8 dq10 dq12 v dd q dq15 v ss v ss q dq25 dq30 nc a3 a6 nc a9 nc v ss dq9 dq14 v ss q v ss v dd v dd q dq22 dq17 nc a2 a10 nc ba0 cas# v dd dq6 dq1 v dd q v dd dq21 dq19 v dd q v dd q v ss q v dd a1 a11 ras# dqm0 v ss q v dd q v dd q dq4 dq2 dq23 v ss q dq20 dq18 dq16 dqm2 a0 ba1 cs# we# dq7 dq5 dq3 v ss q dq0 a b c d e f g h j k l m n p r
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 8 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram ball descriptions ball descriptions table 4: ball descriptions 90-ball vfbga symbol type description j1 clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also increments the internal burst counter and contro ls the output registers. j2 cke input clock enable: cke activates (high) an d deactivates (low) the clk signal. deactivating the cloc k provides precharge power-down and self refresh operation (all banks idle), active power-down (row active in any bank), deep power down (all banks idle), or clock suspend operation (burst/access in progress). cke is synchronous except after the device enters power-down and self refresh modes, where cke becomes asynchronous until after exiting the same mode. th e input buffers, including clk, are disabled during power-down and self refresh modes, providing low standby power. j8 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands ar e masked when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is considered part of the command code. j9, k7, k8 ras#,cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered. k9, k1, f8, f2 dqm0-3 input input/output mask: dqm is sampled high and is an input mask signal for write accesses and an output enable sign al for read accesses. input data is masked during a write cycle. the outp ut buffers are placed in a high-z state (two-clock latency) when during a read cycle. dqm0 corresponds to dq0-dq7, dqm1 corresponds to dq8- dq15, dqm2 corresponds to dq16- dq23, and dqm3 corresponds to dq 24-dq31. dqm0-3 are considered same state when referenced as dqm. j7, h8 ba0, ba1 input bank address input(s): ba0 and ba1 define to which bank the active, read, write, or precharge command is being applied. these balls also provide the op-code during a load mode register command g8, g9, f7, f3, g1, g2, g3, h1, h2, j3, g7,h9 a0?a11 input address inputs: a0?a11 are sampled during the active command (row- address a0?a11) and read/write command (column-address a0?a8; with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine if all banks are to be precharged (a10 high) or bank selected by ba0, ba1. the address in puts also provide the op-code during a load mode register command. r8, n7, r9, n8, p9, m8, m7, l8, l2, m3, m2, p1, n2, r1, n3, r2, e8, d7, d8, b9, c8, a9, c7, a8, a2, c3, a1, c2, b1, d2, d3, e2 dq0?dq31 i/o data input/output: data bus. e3, e7, h3, h7, k2, k3 nc ? internally not connected: these could be left unconnected, but it is recommended they be connected to vss. h3 is a no connect for this part, but may be used as a12 in future designs. b2, b7, c9, d9, e1, l1, m9, n9, p2, p7 v dd q supply dq power: provide isolated power to dqs for improved noise immunity. b3, b8, c1, d1, e9, l9, m1, n1, p3, p8 v ss q supply dq ground: provide isolated ground to dqs for improved noise immunity. a7, f9, l7, r7 v dd supply core power supply. a3, f1, l3, r3 v ss supply ground.
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 9 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram functional description functional description in general, the 256mb sdrams (2 meg x 32 x 4 banks) are quad-bank drams that oper- ate at 3.3v, 2.5v, and 1.8v and include a synchr onous interface (all signals are registered on the positive edge of the clock signal, clk). each of the 67,108,864-bit banks is orga- nized as 4,096 rows by 512 columns by 32 bits. read and write accesses to the sdram are bu rst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registrati on of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the ba nk and row to be a ccessed (ba0 and ba1 select the bank, a0?a11 select the row). the address bits (a0?a8) registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the sdram must be initialized. the following sections pro- vide detailed information covering device initialization, register definition, command descriptions, and device operation. initialization sdrams must be powered up and initialize d in a predefined manner. operational pro- cedures other than those specified may result in undefined operation. once the power is applied to v dd and v dd q (simultaneously) and the clock is stable (stable clock is defined as a signal cycling wi thin timing constrai nts specified for the clock ball), the sdram requires a 100s delay prior to is suing any command other than a command inhibit or nop. starting at some point during this 100s period an d continuing at least through the end of this period, command inhibit or nop commands should be applied. once the 100s delay has been satisfied with at least one command inhibit or nop command having been applied, a precharge command should be applied. all banks must then be precharged, thereby placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. after the auto refresh cycles are complete, the sdram is ready for mode register programming. because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. register definition mode register in order to achieve low power consumption, there are two mode registers in the compo- nent: mode register and extended mode register . extended mode register is illustrated in figure 5. the mode register is used to de fine the specific mode of operation of the sdram. this definition includes the select ion of a burst length, a burst type, a cas latency, an operating mode and a write burs t mode, as shown in figure 3. the mode reg- ister is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power. mode register bits m0?m2 specify the burst length, m3 specifies the type of burst (sequential or interleaved), m4?m6 specify the cas latency, m7 and m8 specify the operating mode, m9 specifies the write burs t mode, and m10 and m11 should be set to zero. m12 and m13 should be set to zero to prevent the extended mode register from being programmed. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requirements will result in unspecified operation.
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 10 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram register definition burst length read and write accesses to the sdram are bu rst oriented, with th e burst length being programmable, as shown in figure 3. the burst length determines the maximum num- ber of column locations that can be ac cessed for a given read or write command. burst lengths of 1, 2, 4, or 8 locations are avai lable for both the sequential and the inter- leaved burst types, and a full -page burst is available for th e sequential type. the full- page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the bl ock if a boundary is reached. the block is uniquely selected by a1?a8 when bl = 2, a2?a8 when bl = 4, and a3?a8 when bl = 8. the remaining (least significant) address bit(s) is (are ) used to select the starting location within the block. full-page bursts wrap wi thin the page if the boundary is reached. burst type accesses within a given burst ma y be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is de termined by the burst length, the burst type, and the starting column address, as shown in table 4.
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 11 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram register definition figure 3: mode register definition 10 m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleaved cas latency reserved 1 2 3 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 op mode a10 reserved* wb 0 1 write burst mode programmed burst length single location access m9 *should program m10 = ?0, 0? to ensure compatibility with future devices. ba0 ba1 m9 m7 m6 m5 m4 m3 m8 m2 m1 m0 m10 11 a11 m11 m12 m13 0 0 13 12
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 12 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram register definition notes: 1. for full-page accesses: y = 512. 2. for bl = 2, a1 ? a8 select the block-of-two burst; a0 selects the starting column within the block. 3. for bl = 4, a2 ? a8 select the block-of-four burst; a0-a 1 select the starting column within the block. 4. for bl = 8, a3 ? a8 select the block-of-eight burst; a0-a 2 select the starti ng column within the block. 5. for a full-page burst, the full row is selected and a0 ? a8 select the starting column. 6. whenever a boundary of the block is reache d within a given sequence above, the follow- ing access wraps within the block. 7. for bl = 1, a0 ? a8 select the unique column to be ac cessed, and mode register bit m3 is ignored. cas latency the cas latency is the delay, in clock cycles, between the registration of a read com- mand and the availability of the first piece of output data. the latency can be set to one, two, or three clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by clock edge n + m . the dqs will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the re levant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0 table 5: burst definition table burst length order of accesses within a burst starting column address type = sequential type = interleaved 2a0 00-1 0-1 11-0 1-0 4a1a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8a2a1a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page (y) n = a0-a11/9/8 (location 0-y) cn, cn + 1, cn + 2 cn + 3, cn + 4... ?cn - 1, cn? not supported
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 13 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram register definition and the latency is programmed to two clocks, the dqs will start driving after t1 and the data will be valid by t2, as shown in figure 4. table 5 indicates the operating frequencies at which each cas latency setting can be used. reserved states should not be used as unkn own operation or incomp atibility with future versions may result. operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combi- nations of values for m7 and m8 are reserved for future use and/or test modes. the pro- grammed burst length applies to both read and write bursts. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m0-m2 applies to both read and write bursts; when m9= 1, the programmed bu rst length applies to read bursts, but write accesses are single-location (nonburst) accesses. low-power extended mode register definition the low-power extended mode register controls the functions beyond those controlled by the mode register. these additional functions are special features of the mobile device. they include temperature compensated self refresh (tcsr) control, partial array self refresh (pasr), and output drive stre ngth. not programming the extended mode register upon initialization will result in default settings for the low-power features. the extended mode will default with the temperature sensor enabled, full drive strength, and full array refresh. the low-power extended mode register is programmed via the mode register set command (ba1 = 1, ba0 = 0) and retains the stored information until it is programmed again or the device loses power.
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 14 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram register definition figure 4: cas latency table 6: cas latency speed allowable operating frequency (mhz) cl = 1 cl = 2 cl = 3 -75 ? 104 133 - 8 50 104 125 -10 50 83.3 100 c lk dq t2 t1 t3 t0 c l = 3 lz d out t oh t c ommand nop read t a c nop t4 nop don?t c are undefined c lk dq t2 t1 t0 c l = 1 lz d out t oh t c ommand nop read t a c c lk dq t2 t1 t3 t0 c l = 2 lz d out t oh t c ommand nop read t a c nop
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 15 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram register definition figure 5: low power ext ended mode register table notes: 1. e13 and e12 (ba1 and ba0) must be ?1, 0? to select the extended mode register (vs. the base mode register). 2. default emr values are full arra y for pasr, full drive strength. 3. rfu: reserved for future use. 4. e4 and e3 are ?don?t care.? the low-power extended mode register must be programmed with e7 through e11 set to ?0?. it must be loaded when all banks are id le and no bursts are in progress, and the con- troller must wait the specified time before in itiating any subsequent operation. violating either of these requirements results in un specified operation. once the values are entered, the extended mode re gister settings will be retained even after exiting deep power-down mode. temperature compensated self refresh temperature compensated self refresh (tcsr) allows the controller to program the refresh interval during self refresh mode, according to the case temperature of the mobile device. this allows great power savings during self refresh during most operating temperature ranges. only during extreme te mperatures would the controller have to select the maximum tcsr level. this wo uld guarantee data during self refresh. every cell in the dram requires refreshing due to the capacitor losing its charge over time. the refresh rate is dependent on temperature. at higher temperatures a capacitor loses charge quicker than at lower temperatur es, requiring the cells to be refreshed more often. historically, during self refresh, the refresh rate has been set to accommodate the worst case, or highest temperature range expected. a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 low power extended mode register (ex) address bus 976543 8210 a10 a11 10 11 12 pasr 0 0 0 13 1 all must be set to "0" ba0 e9 e7 e6 e5 e4 e3 e8 e2 e1 e0 e10 e11 e12 ba1 e13 1 self refresh coverage four banks 2 two banks (bank 0,1) one bank (bank 0) rfu 3 rfu 1/2 bank (bank 0) 1/4 bank (bank 0) rfu e0 0 0 0 1 1 1 0 1 e1 0 0 0 1 1 1 0 1 e2 0 0 0 0 1 1 1 1 ds driver strength full strength 2 half strength rfu rfu e6 e5 0 0 1 1 0 1 0 1 e4 e3 must be set to "0" 0 0
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 16 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram register definition thus, during ambient temperatures, the po wer consumed during refresh was unneces- sarily high because the refresh rate was se t to accommodate the higher temperatures. this sdram has an on-chip temperature sensor that automatically adjusts refresh rate according to die temperature. the default se tting for the tcsr is with the temperature sensor enabled. partial array self refresh for further power savings during self refresh, the partial array self refresh (pasr) feature allows the controller to select the amount of memory that will be refreshed during self refresh. the refresh options are all banks (banks 0, 1, 2, and 3), two banks (banks 0 and 1), and one bank (bank 0). also included in the refresh options are the half-bank and quarter-bank partial array self refresh (b ank 0). write and read commands occur to any bank selected during standard operation, but only the selected banks in pasr will be refreshed during self refresh. it is important to note that data in banks 2 and 3 will be lost when the two bank option is used. data will be lost in banks 1, 2, and 3 when the one bank option is used. driver strength bits e5 and e6 of the extended mode register can be used to select the driver strength of the dq outputs. this value should be set according to the application?s requirements. full drive strength was carried over from standard sdram and is suitable to drive higher load systems.
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 17 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram commands commands table 7 provides a quick reference of available commands. this is followed by a written description of each command. three addition al truth tables appear following "opera- tion" on page 21; these tables provid e current state/next state information. notes: 1. a0?a11 provide row address, and ba0, ba1 determine which bank is made active. 2. a0?a8 provide column address; a10 high enables the auto precharge feature (non persis- tent), while a10 low disables the auto precharge feature; ba0, ba1 determine which bank is being read from or written to. 3. this command is burst terminate when ck e is high and deep power down when cke is low. 4. the purpose of the burst terminate command is to stop a data burst, thus the com- mand could coincide with data on the bus. however the dqs column reads a don?t care state to illustrate that the burst terminate command can occu r when there is no data present. 5. a10 low: ba0, ba1 determine the bank being precharged. a10 high: all banks pre- charged and ba0, ba 1 are ?don?t care.? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addr essing; all inputs and i/os are ?don?t care? except for cke. 8. a0?a11 define the op-code written to the mode and extend ed mode register. 9. activates or deactivates the dqs during wri tes (zero-clock delay) and reads (two-clock delay). dqm0 controls dq0?dq7; dqm1 cont rols dq8?dq15; dqm2 controls dq16?dq23; and dqm3 cont rol dq24?dq31. command inhibit the command inhibit function prevents ne w commands from being executed by the sdram, regardless of whether the clk signal is enabled. the sdram is effectively dese- lected and the dq balls tri-state. operatio ns already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to an sdram which is selected (cs# is low). this prevents unwanted commands from being registered during idle or wait states. operations al ready in progress are not affected. table 7: truth table ? co mmands and dqm operation cke is high for all commands shown ex cept self refresh and deep power down name (function) cs# ras# cas# we# dqm addr dqs notes command inhibit (nop) hx xx x x x no operation (nop) lhhh x x x active (select bank and activate row) l l h h x bank/row x 1 read (select bank and column, and start read burst) lhlhl/h 8 bank/col x 2 write (select bank and colu mn, and start write burst) l h l l l/h 8 bank/col valid 2 burst terminate or deep power down (enter deep power-down mode) lhhl x x x 3, 4 precharge (deactivate row in bank or banks) l l h l x code x 5 auto refresh or self refresh (enter self refresh mode) ll lhx x x 6, 7 load mode register l l l l x op-code x 8 write enable/output enable x x x x l x active 9 write inhibit/output high-z xx xx h x high-z9
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 18 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram commands load mode register the mode register is loaded via inputs a0, ba0, and ba1. (see "mode register" on page 9.) the load mode register and load extended mode register commands can only be issued when all banks are idle , and a subsequent executable command can- not be issued until t mrd is met. the values of the load mode register and exte nded mode register will be retained even when exiting deep power-down mode. active the active command is used to open (or acti vate) a row in a particular bank for a sub- sequent access. the value on the ba0, ba1 inputs selects the bank, and the address pro- vided on inputs a0?a11 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a diffe rent row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a8 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be pre- charged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. read da ta appears on the dqs subject to the logic level on the dqm inputs two clocks earlier. if a given dqm signal was registered high, the corresponding dqs will be high-z two clocks later; if the dqm signal was registered low, the dqs will provide valid data. write the write command is used to initiate a burs t write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a8 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be pre- charged at the end of the write burst; if au to precharge is not selected, the row will remain open for subsequent accesses. input da ta appearing on the dqs is written to the memory array subject to the dqm input logi c level appearing coincident with the data. if a given dqm signal is registered low, the corresponding data will be written to mem- ory; if the dqm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select th e bank. otherwise ba0, ba1 are treated as ?don?t care.? once a bank has been precharged , it is in the idle st ate and must be acti- vated prior to any read or write commands being issued to that bank. auto precharge auto precharge is a feature which performs the same individual-bank precharge func- tion described above, without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write com- mand. a precharge of the bank/row that is addressed with the read or write com-
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 19 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram commands mand is automatically performed upon comple tion of the read or write burst, except in the full-page burst mode, where auto precharge does not apply. auto precharge is non persistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that the precharge is in itiated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge time ( t rp) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, as desc ribed for each burst type in "operation" on page 21. burst terminate the burst terminate command is used to tr uncate either fixed-length or full-page bursts. the most recently re gistered read or write command prior to the burst ter- minate command will be truncated, as shown in "operation" on page 21. auto refresh auto refresh is used during normal oper ation of the sdram and is analogous to cas#-before-ras# (cbr) refresh in conven tional drams. this command is non per- sistent, so it must be issued each time a refresh is required. all active banks must be precharged prior to issuing an auto refresh command. the auto refresh command should not be issued until the minimum t rp has been met after the pre- charge command, as shown in "operation" on page 21. the addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto refr esh command. the 256mb sdram requires 4,096 auto refresh cycles every 64ms ( t ref). providing a distributed auto refresh command every 15.625s will meet th e refresh requirement and ensure that each row is refreshed. alternatively, 4,096 auto refresh commands can be issued in a burst at the minimum cycle rate ( t rfc), once every 64ms. self refresh the self refresh command can be used to retain data in the sdram, even if the rest of the system is powered down. when in th e self refresh mode, the sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command, except cke is disabled (low). once the self refresh command is registered, all the inputs to the sdram become ?don?t care? with the exception of cke, which must remain low. once self refresh mode is engaged, the sdram provides its own internal clocking, caus- ing it to perform its own auto refresh cycles. the sdram must remain in self refresh mode for a minimum period equal to t ras and may remain in self refresh mode for an indefinite period beyond that. the procedure for exiting self refresh requires a sequence of commands. first, clk must be stable (stable clock is defi ned as a signal cycling within timing constr aints specified for the clock ball) prior to cke going back high. once cke is high, the sdram must have nop commands issued (a minimum of two clocks) for t xsr because time is required for the completion of an y internal refresh in progress. upon exiting the self refresh mode, auto refresh commands must be issued every 15.625s or less as both self refresh an d auto refresh utilize the row refresh counter.
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 20 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram commands deep power-down deep power-down is an operating mode to achieve maximum power reduction by eliminating the power of the whole memory arra y of the devices. array data will not be retained once the device enters deep power-down mode. the settings in the mode and extended mode register will be retained during deep power-down. this mode is entered by having all banks idle then cs# and we# held low with ras# and cas# held high at the rising edge of the clock, while cke is low. this mode is exited by asserting cke high.
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 21 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram operation operation bank/row activation before any read or write commands can be issued to a bank within the sdram, a row in that bank must be ?opened.? this is accomplished via the active command, which selects both the bank and the row to be activated (see figure 5 on page 15). after opening a row (issuing an active command), a read or write command may be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specification of 20ns with a 125 mhz clock (8ns period) results in 2.5 clocks, rounded to 3. this is reflected in figure 6 on page 21, which covers any case where 2 < t rcd (min)/ t ck 3. (the same procedure is used to convert other specification limits from time units to clock cycles.) a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?clo sed? (precharged). the minimum time inter- val between successive active commands to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the mini- mum time interval between su ccessive active commands to different banks is defined by t rrd. figure 6: activating a spec ific row in a specific bank cs # we# c a s # ra s # c ke c lk a0-a11 row addre ss dont c are hi g h ba0, ba1 bank addre ss
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 22 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram operation figure 7: example: meeting t rcd (min) when 2 < t rcd (min)/ t ck < 3 reads read bursts are initiated with a re ad command, as shown in figure 8. the starting column and bank addresses are provided with the read command, and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the generic read commands used in the following illustrations, auto precharge is disabled. during read bursts, the valid data-out element from the starting column address will be available following the cas latency afte r the read command. each subsequent data- out element will be valid by the next positive clock edge. figure 9 shows general timing for each possible cas latency setting. c lk t2 t1 t3 t0 t c ommand nop a c tive read or write nop r c d (min) t c k t c k t c k don ? t c are
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 23 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram operation figure 8: read command upon completion of a burst, assuming no other commands have been initiated, the dqs will go high-z. a full-page burst will continue until terminated. (at the end of the page, it will wrap to column 0 and continue.) data from any read burst may be truncate d with a subsequent read command, and data from a fixed-length read burst may be immediately followed by data from a read command. in either case, a continuous flow of data can be maintained. the first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. the new read com- mand should be issued x cycles before the clock edge at which the last desired data ele- ment is valid, where x equals the cas latency minus one. cs# we# cas# ras# cke clk column address a10 ba0,ba1 don?t care high enable auto precharge disable auto precharge bank address a0?a8 a9, a11
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 24 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram operation figure 9: cas latency this is shown in figure 10 for cas latencies of one, two, and three; data element n + 3 is either the last of a burst of four or the la st desired of a longer burst. the 256mb sdram uses a pipelined architecture and therefore does not require the 2 n rule associated with a prefetch architecture. a read command can be initiated on any clock cycle following a previous read command. full-speed random read accesses can be performed to the same bank, as shown in figure 10 on page 2 5, or each subsequent read may be per- formed to a different bank. c lk dq t2 t1 t3 t0 c l = 3 lz d out t oh t c ommand nop read t a c nop t4 nop don ? t c are undefined c lk dq t2 t1 t0 c l = 1 lz d out t oh t c ommand nop read t a c c lk dq t2 t1 t3 t0 c l = 2 lz d out t oh t c ommand nop read t a c nop
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 25 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram operation figure 10: consec utive read bursts note: each read command may be to either bank. dqm is low. c lk dq d out n t2 t1 t4 t3 t5 t0 c ommand addre ss read nop nop nop bank, c ol n nop bank, c ol b d out n + 1 d out n + 2 d out n + 3 d out b read x = 0 c y c les c l = 1 c lk dq d out n t2 t1 t4 t3 t 6 t5 t0 c ommand addre ss read nop nop nop nop bank, c ol n nop bank, c ol b d out n + 1 d out n + 2 d out n + 3 d out b read x = 1 c y c le c l = 2 c lk dq d out n t2 t1 t4 t3 t 6 t5 t0 c ommand addre ss read nop nop nop nop bank, c ol n nop bank, c ol b d out n + 1 d out n + 2 d out n + 3 d out b read nop t7 x = 2 c y c les c l = 3 don ? t c are
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 26 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram operation figure 11: random read accesses note: each read command may be to either bank. dqm is low. data from any read burst may be truncated with a subsequent write command, and data from a fixed-length read burst may be immediately followed by data from a write command (subject to bus turnaround limitations). the write burst may be clk dq t2 t1 t4 t3 t6 t5 t0 command address read nop nop bank, col n don?t care d out n d out a d out x d out m read note: each read command may be to either bank. dqm is low. read read nop bank, col a bank, col x bank, col m clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop bank, col n d out a d out x d out m read read read nop bank, col a bank, col x bank, col m cas latency = 2 cas latency = 3 clk dq d out n t2 t1 t4 t3 t0 command address read nop bank, col n d out a d out x d out m read read read bank, col a bank, col x bank, col m cas latency = 1
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 27 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram operation initiated on the clock edge immediately follow ing the last (or last desired) data element from the read burst, provided that i/o cont ention can be avoided. in a given system design, there may be a possibility that the de vice driving the input data will go low-z before the sdram dqs go high-z. in this case, at least a single-cycle delay should occur between the last read data and the write command. the dqm input is used to avoid i/o contenti on, as shown in figure 11 on page 26 and figure 12 on page 28. the dqm signal must be asserted (high) at least two clocks prior to the write command (dqm latency is two cl ocks for output buffers) to suppress data- out from the read. once the write command is registered, the dqs will go high-z (or remain high-z), regardless of the state of the dqm signal, provided the dqm was active on the clock just prior to the write command that truncated the read command. if not, the second write will be an invalid write. for example, if dqm was low during t4 (in figure 13) then the writes at t5 an d t7 would be valid, while the write at t6 would be invalid. the dqm signal must be de-asserted prior to the write command (dqm latency is zero clocks for input buffers) to ensure that the written data is not masked. figure 12 shows the case where the clock frequency allo ws for bus contention to be avoided with- out adding a nop cycle, and figure 13 shows the case where the additional nop is needed. a fixed-length read burst may be followed by, or truncated with, a precharge com- mand to the same bank (provided that auto precharge was not activated), and a full- page burst may be truncated with a precha rge command to the same bank. the pre- charge command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 13 on page 28 for each possible cas latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. following the precharge com- mand, a subsequent command to the same bank cannot be issued until t rp is met. note that part of the row precharg e time is hidden du ring the access of the last data ele- ment(s). in the case of a fixed-length burst being executed to completion, a precharge com- mand issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. the disadvan- tage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed-length or full-page bursts.
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 28 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram operation figure 12: read to write note: cl = 3. the read command may be to any bank, and the write command may be to any bank. if a burst of one is used, then dqm is not required. figure 13: read to wr ite with extra clock cycle note: cl = 3. the read command may be to any bank, and the write command may be to any bank. don?t care read nop nop write nop clk t2 t1 t4 t3 t0 dqm dq d out n command d in b address bank, col n bank, col b ds t hz t t ck don?t care read nop nop nop nop dqm clk dq d out n t2 t1 t4 t3 t0 command address bank, col n write d in b bank, col b t5 ds t hz t
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 29 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram operation figure 14: read to precharge note: dqm is low. full-page read bursts can be truncate d with the burst terminate command, and fixed-length read bursts may be trunca ted with a burst terminate command, pro- vided that auto precharge was not activated. the burst terminate command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 15 for each possible cas latency; data element n + 3 is the last desired data element of a longer burst. clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank a , col n nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 bank a , row bank ( a or all) don?t care x = 0 cycles cl = 1 x = 1 cycle cl = 2 cl = 3 bank a , col n bank a , row bank ( a or all) bank a , col n bank a , row bank ( a or all) x = 2 cycles
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 30 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram operation figure 15: terminating a read burst note: dqm is low. don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop t7 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop x = 0 cycles cl = 1 x = 1 cycle cl = 2 cl = 3 x = 2 cycles
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 31 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram operation writes write bursts are initiated with a write command, as shown in figure 15 on page 30. the starting column and bank addresses are provided with the write command, and auto precharge is either enabled or disabled fo r that access. if auto precharge is enabled, the row being accessed is precharged at th e completion of the burst. for the generic write commands used in the following illu strations, auto precharge is disabled. during write bursts, the first valid data-in element will be registered coincident with the write command. subsequent data elements will be registered on each successive positive clock edge. upon co mpletion of a fixed-length bu rst, assuming no other com- mands have been initiated, the dqs will remain high-z and any additional input data will be ignored (see figure 17). a full-page burst will continue until terminated. (at the end of the page, it will wrap to column 0 and continue.) figure 16: write command data for any write burst may be truncated with a subsequent write command, and data for a fixed-length write burst may be immediately followed by data for a write command. the new write command can be issued on any clock following the previous write command, and the data provided coincident with the new command applies to the new command. an example is shown in figure 17 on page 32. data n + 1 is either the last of a burst of two or the last desired of a longer burst. the 256mb sdram uses a pipe- lined architecture and therefore does not requ ire the 2n rule associated with a prefetch architecture. a write command can be initiated on any clock cycle following a previous cs# we# cas# ras# cke clk column address don?t care high enable auto precharge disable auto precharge bank address a0?a8 a10 ba0, 1 a9, a11 valid address
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 32 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram operation write command. full-speed random write acce sses within a page can be performed to the same bank, as shown in figure 19, or each subsequent write may be performed to a different bank. figure 17: write burst note: bl = 2. dqm is low. figure 18: write to write note: dqm is low. each write command may be to any bank. data for any write burst may be truncate d with a subsequent read command, and data for a fixed-length write burst may be immediately followed by a read command. once the read command is registered, the data inputs will be ignored, and writes will not be executed. an example is shown in figure 19 on page 33. data n + 1 is either the last of a burst of two or the last desired of a longer burst. data for a fixed-length write burst may be followed by, or truncated with, a pre- charge command to the same bank (provided that auto precharge was not activated), and a full-page write burst may be trun cated with a precharge command to the same bank. the precharge co mmand should be issued t wr after the clock edge at which the last desired input data element is registered. the auto precharge mode requires a t wr of at least one clock plus time, regardless of frequency. clk dq d in n t2 t1 t3 t0 command address nop nop don?t care write d in n + 1 nop bank, col n clk dq t2 t1 t0 command address nop write write bank, col n bank, col b d in n d in n + 1 d in b don?t care
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 33 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram operation in addition, when truncating a write burst, the dqm signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the pre- charge command. an example is shown in figure 21. data n + 1 is either the last of a burst of two or the last desired of a long er burst. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. in the case of a fixed-length burst being executed to completion, a precharge com- mand issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. the disadvan- tage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed-length or full-page bursts. figure 19: random write cycles note: each write command may be to any bank. dqm is low. figure 20: write to read note: the write command may be to any bank, and the read command may be to any bank. dqm is low. cl = 2 for illustration. don?t care clk dq d in n t2 t1 t3 t0 command address write bank, col n d in a d in x d in m write write write bank, col a bank, col x bank, col m don?t care clk dq t2 t1 t3 t0 command address nop write bank, col n d in n d in n + 1 d out b read nop nop bank, col b nop d out b + 1 t4 t5
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 34 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram operation figure 21: write to precharge note: dqm could remain low in this example if the write burst is a fixed length of two. fixed-length or full-page write bursts can be truncated with the burst terminate command. when truncating a write burst, the input data applied coincident with the burst terminate command will be ignored. the last data written (provided that dqm is low at that time) will be the inpu t data applied one clock previous to the burst terminate command. this is shown in figure 22, where data n is the last desired data element of a longer burst. precharge the precharge command (see figure 23) is us ed to deactivate the open row in a par- ticular bank or the open row in all banks. th e bank(s) will be available for a subsequent row access some specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 are treated as ?don?t care.? once a bank has been pre- charged, it is in the idle state and must be activated pr ior to any read or write com- mands being issued to that bank. don?t care dqm clk dq t2 t1 t4 t3 t0 command address bank a , col n t5 nop write precharge nop nop d in n d in n + 1 active t rp bank ( a or all) t wr bank a , row dqm dq command address bank a , col n nop write precharge nop nop d in n d in n + 1 active t rp bank ( a or all) t wr bank a , row t6 nop nop t wr@ t ck < 15ns t wr@ t ck 15ns
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 35 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram operation power-down power-down occurs if cke is registered low coincident with a nop or command inhibit when no accesses are in progress. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and outp ut buffers, excludin g cke, for maximum power savings while in standby. the device may not remain in the power-down state longer than the refresh period (64ms) sinc e no refresh operations are performed in this mode. the power-down state is exited by regi stering a nop or command inhibit and cke high at the desired clock edge (meeting t cks). see figure 24. deep power-down deep power-down mode is a maximum power savings feature achieved by shutting off the power to the entire memory array of the device. data on the memory array will not be retained once deep power-down mode is executed. deep power-down mode is entered by having all banks idle then cs# and we# held low with ras# and cas# high at the rising edge of the clock, while cke is low. cke must be held low during deep power down. figure 22: terminating a write burst note: dqms are low. don?t care clk dq t2 t1 t0 command address bank, col n write burst terminate next command d in n (address) (data)
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 36 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram operation figure 23: pr echarge command figure 24: power-down in order to exit deep power-down mode, cke must be asserted high. after exiting, the following sequence is needed in order to enter a new command: 1. maintain nop input conditions for a minimum of 100us. 2. issue precharge commands for all banks. 3. issue two or more auto refresh commands. the values of the mode register and extended mode register will be retained upon exit deep power down. cs# we# cas# ras# cke clk a10 don?t care high all banks bank selected a0-a9, a11 ba0,1 bank address valid address don?t care t ras t rcd t rc all banks idle input buffers gated off exit power-down mode. ( ) ( ) ( ) ( ) ( ) ( ) t cks > t cks command nop active enter power-down mode. nop clk cke ( ) ( ) ( ) ( )
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 37 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram operation clock suspend the clock suspend mode occurs when a column access/burst is in progress and cke is registered low. in the clock suspend mode, the internal clock is deactivated, ?freezing? the synchronous logic. for each positive clock edge on which cke is sampled low, the next internal positive clock edge is suspended. any command or data present on the input balls at the time of a suspended internal clock edge is ignored; any data present on the dq balls remains driven; and burst counters are not incremented, as long as the clock is suspended. (see examples in figure 25 and figure 26.) clock suspend mode is exited by registerin g cke high; the internal clock and related operation will resume on the subsequent positive clock edge. burst read/single write the burst read/single write mode is entered by programming the write burst mode bit (m9) in the mode register to a logic 1. in this mode, all write commands result in the access of a single column location (burst of one), regardless of the programmed burst length. read commands access columns ac cording to the progra mmed burst length and sequence, just as in the normal mode of operation (m9 = 0). concurrent auto precharge an access command (read or write) to a se cond bank while an access command with auto precharge enabled on a first bank is executing is not allowed by sdrams, unless the sdram supports concurrent auto precha rge. micron sdrams support concurrent auto precharge. four cases where concurrent auto precharge occurs are defined below. read with auto precharge 1. interrupted by a read (with or without auto precharge): a read to bank m will inter- rupt a read on bank n , cas latency later. the precharge to bank n will begin when the read to bank m is registered (figure 27). 2. interrupted by a write (with or with out auto precharge): a write to bank m will interrupt a read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered (figure 28).
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 38 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram operation figure 25: clock susp end during write burst note: for this example, bl = 4 or greater, and dm is low. figure 26: clock susp end during read burst note: for this example, cl = 2, bl = 4 or greater, and dqm is low. don?t care d in command address write bank, col n d in n nop nop clk t2 t1 t4 t3 t5 t0 cke internal clock nop d in n + 1 d in n + 2 don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 cke internal clock nop
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 39 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram operation figure 27: read with auto precharge interrupted by a read note: dqm is low. figure 28: read with auto pr echarge interrupted by a write note: dqm is high at t2 to prevent d out - a +1 from contending with d in - d at t4. don?t care clk dq d out a t2 t1 t4 t3 t6 t5 t0 command read - ap bank n nop nop nop nop d out a + 1 d out d d out d + 1 nop t7 bank n cl = 3 (bank m ) bank m address idle nop bank n , col a bank m , col d read - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active read with burst of 4 precharge rp - bank n t rp - bank m cl = 3 (bank n ) clk dq d out a t2 t1 t4 t3 t6 t5 t0 command nop nop nop nop d in d + 1 d in d d in d + 2 d in d + 3 nop t7 bank n bank m address idle nop dqm bank n , col a bank m , col d write - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active write with burst of 4 write-back rp - bank n t wr - bank m cl = 3 (bank n ) read - ap bank n 1 don?t care
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 40 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram operation write with auto precharge 3. interrupted by a read (with or without auto precharge): a read to bank m will inter- rupt a write on bank n when registered, with the data-out appearing cas latency later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in regis- tered one clock prior to the read to bank m (figure 29). 4. interrupted by a write (with or with out auto precharge): a write to bank m will interrupt a write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid data write to bank n will be data registered one clock prior to a write to bank m (figure 30). figure 29: write with auto precharge interrupted by a read note: dqm is low. figure 30: write with auto pr echarge interrupted by a write note: dqm is low. don?t care clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in a + 1 d in a nop nop t7 bank n bank m address bank n , col a bank m , col d read - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active read with burst of 4 t t rp - bank m d out d d out d + 1 cl = 3 (bank m ) rp - bank n wr - bank n don?t care clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in d + 1 d in d d in a + 1 d in a + 2 d in a d in d + 2 d in d + 3 nop t7 bank n bank m address nop bank n , col a bank m , col d write - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active write with burst of 4 write-back wr - bank n t rp - bank n t wr - bank m
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 41 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram truth tables truth tables notes: 1. cke n is the logic state of cke at clock edge n; cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the sd ram immediately prior to clock edge n . 3. command n is the command registered at clock edge n , and action n is a result of com- mand n . 4. all states and sequences not shown are illegal or reserved. 5. exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that t cks is met). 6. exiting self refresh at clock edge n will put the device in the all banks idle state once t xsr is met. command inhibit or nop commands sh ould be issued on any clock edges occur- ring during the t xsr period. a minimum of two nop co mmands must be provided during t xsr period. 7. after exiting clock suspend at clock edge n , the device will resume operation and recog- nize the next command at clock edge n + 1. 8. deep power-down is power savings feature of this mobile sdram device. this command is burst terminate when cke is high and deep power down when cke is low. table 8: truth table ? cke notes: 1?4 cke n-1 cke n current state command n action n notes l l power-down x mai ntain power-down self refresh x maintain self refresh clock suspend x maintain clock suspend deep power-down x maint ain deep power-down 8 l h power-down command inhibit or nop exit power-down 5 deep power-down x exit deep power-down 8 self refresh command inhibit or nop exit self refresh 6 clock suspend x exit clock suspend 7 h l all banks idle command inhibit or nop power-down entry all banks idle burst termi nate deep power-down entry 8 all banks idle auto refresh self refresh entry reading or writing valid clock suspend entry h h see truth table 3
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 42 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram truth tables notes: 1. this table applies when cke n-1 was high and cke n is high (see truth table 2) and after t xsr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown ar e those allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3. current state definitions: idle : the bank has been precharged, and t rp has been met. row active : a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no regist er accesses are in progress. read : a read burst has been initiated, with auto precharge disabled, and has not yet ter- minated or been terminated. write : a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. the following states must not be interrupt ed by a command issued to the same bank. command inhibit or nop command s, or allowable commands to the other bank should be issued on any clock edge occurring duri ng these states. allo wable commands to the other bank are determined by its current state and truth table 3, and according to truth table 4. precharging : starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. row activating : starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the row active state read w/auto precharge enabled : starts with registration of a read command with auto precharge enab led and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto precharge enabled : starts with registration of a write command with auto precharge enab led and ends when t rp has been met. once t rp is met, the bank will be in the idle state. table 9: truth table ? current state bank n , command to bank n notes: 1?6; notes appear below table current state cs# ras# cas# we# command (action) notes any h x x x command inhibit (nop/conti nue previous operation) lhhh no operation (nop/continue previous operation) idle l l h h active (select and activate row) lllh auto refresh 7 llll load mode register 7 llhl precharge 11 row activelhlh read (select column and start read burst) 10 lhl l write (select column and start write burst) 10 llhl precharge (deactivate row in bank or banks) 8 read (auto precharge disabled) lhlh read (select column and start new read burst) 10 lhl l write (select column and start write burst) 10 llhl precharge (truncate read burst, start precharge) 8 lhhl burst terminate 9 lhhl deep power down 9 write (auto precharge disabled) lhlh read (select column and start read burst) 10 lhl l write (select column an d start new write burst) 10 llhl precharge (truncate writ e burst, start precharge) 8 lhhl burst terminate 9 lhhl deep power-down 9
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 43 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram truth tables 5. the following states must not be inte rrupted by any executable command; command inhibit or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rc is met. once t rc is met, the sdram will be in the all banks idle state. accessing mode register: starts with regi stration of a load mode register command and ends when t mrd has been met. once t mrd is met, the sdram will be in the all banks idle state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks will be in the idle state. 6. all states and sequences not shown are illegal or reserved. 7. not bank-specific; require s that all banks are idle. 8. may or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. this command is burst terminate when ck e is high and deep power down when cke is low. 10. reads or writes listed in the command (act ion) column include reads or writes with auto precharge enabled and reads or wr ites with auto precharge disabled. 11. does not affect the state of the bank and acts as a nop to that bank.
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 44 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram truth tables notes: 1. this table applies when cke n-1 was high and cke n is high (see truth table 2) and after t xsr has been met (if the previous state was self refresh). 2. this table describes al ternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). exceptions are cov- ered in the notes below. 3. current state definitions: idle : the bank has been precharged, and t rp has been met. row active : a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no regist er accesses are in progress. read : a read burst has been initiated, with auto precharge disabled, and has not yet ter- minated or been terminated. write : a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read w/auto precharge enabled : starts with registration of a read command with auto precharge enabled, and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto precharge enabled : starts with registration of a write command with auto precharge enabled, and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 4. auto refresh, self refresh and load mode register commands may only be issued when all banks are idle. 5. a burst terminate command cann ot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved. table 10: truth table ? current state bank n , command to bank m notes: 1?6; notes appear below and on next page current state cs# ras# cas# we# command (action) notes any hxxx command inhibit (n op/continue previous operation) l hhh no operation (nop/conti nue previous operation) idle xxxx any command otherwise allowed to bank m row activating, active, or precharging llhh active (select and activate row) lhlh read (select column and start read burst) 7 lhl l write (select column and start write burst) 7 llhl precharge read (auto precharge disabled) llhh active (select and activate row) lhlh read (select column and start new read burst) 7, 10 lhl l write (select column and start write burst) 7, 11 llhl precharge 9 write (auto precharge disabled) llhh active (select and activate row) lhlh read (select column and start read burst) 7, 12 lhl l write (select column an d start new write burst) 7, 13 llhl precharge 9 read (with auto precharge) llhh active (select and activate row) lhlh read (select column and start new read burst) 7, 8, 14 lhl l write (select column and start write burst) 7,8, 15 llhl precharge 9 write (with auto precharge) llhh active (select and activate row) lhlh read (select column and start read burst) 7,8, 16 lhl l write (select column an d start new write burst) 7,8, 17 llhl precharge 9
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 45 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram truth tables 7. reads or writes to bank m listed in the command (action) column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. concurrent auto precharge: bank n will initiate the auto precharge command when its burst has been interrupted by bank m burst. 9. burst in bank n continues as initiated. 10. for a read without auto precharge interrup ted by a read (with or without auto pre- charge), the read to bank m will interrupt the read on bank n , cas latency later (figure 10 consecutive read bursts). 11. for a read without auto precharge interrup ted by a write (with or without auto pre- charge), the write to bank m will interrupt the read on bank n when registered (figures 12 and 13). dqm should be used one clock prior to the write command to prevent bus contention. 12. for a write without auto precharge interru pted by a read (with or without auto pre- charge), the read to bank m will interrupt the write on bank n when registered (figure 20), with the data-out appearing cas late ncy later. the last valid write to bank n will be data-in registered one clock prior to the read to bank m . 13. for a write without auto precharge interrupt ed by a write (with or without auto pre- charge), the write to bank wi ll interrupt the write on bank n when registered (figure 18). the last valid write to bank n will be data-in registered one clock prior to the read to bank m . 14. for a read with auto precharg e interrupted by a read (with or without auto precharge), the read to bank m will interrupt the read on bank n , cas latency later. the precharge to bank n will begin when the read to bank m is registered. 15. for a read with auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered. 16. for a write with auto precha rge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the write on bank n when registered , with the data- out appearing cas latency late r. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write bank n will be data-in registered one clock prior to the read to bank m . 17. for a write with auto prec harge interrupted by a write (with or without auto pre- charge), the write to bank m interrupt the write on bank n when registered. the pre- charge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the la st valid write to bank n will be data registered one clock to the write to bank m .
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 46 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram electrical specifications electrical specifications absolute maximum ratings stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operationa l sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. table 11: absolute maximum ratings voltage/temperature min max units voltage on v dd /v dd q supply relative to v ss (3.3v) -1 +4.6 v relative to v ss (2.5v) -0.5 +3.6 v relative to v ss (1.8v) -0.35 +2.8 v voltage on inputs, nc or i/o balls relative to v ss (3.3v) -1 +4.6 v relative to v ss (2.5v) -0.5 +3.6 v relative to v ss (1.8v) -0.35 +2.8 v operating temperature t a (commercial) 0 +70 c t a (industrial) -40 +85 c storage temperature plastic -55 +150 c table 12: dc electrical characteristics and opera ting conditions (lc version) notes: 1, 5, 6; note s appear on page 54; v dd = +3.3 0.3v, v dd q = +3.3v 0.3v parameter/condition symbol min max units notes supply voltage v dd 33.6v i/o supply voltage v dd q3 3.6 v input high voltage: logic 1; all input v ih 0.8 x v dd qv dd q + 0.3 v 22 input low voltage: logic 0; all inputs v il -0.3 0.3 v 22 output high voltage: all inputs: iout = -4ma v oh v dd q - 0.2 - v output low voltage: all inputs: iout = 4ma v ol -0.2v input leakage current: any input 0v v in v dd (all other balls not under test = 0v) i i -5 5 a output leakage current: dqs are disabled; 0v v out v dd q i oz -5 5 a
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 47 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram electrical specifications table 13: dc electrical characteristics and opera ting conditions (v version) notes: 1, 5, 6; note s appear on page 54; v dd = +2.5 0.2v, v dd q = +2.5v 0.2v parameter/condition symbol min max units notes supply voltage v dd 2.3 2.7 v i/o supply voltage v dd q2.3 2.7 v input high voltage: logic 1; all inputs v ih 0.8 x v dd qv dd q + 0.3 v 22 input low voltage: logic 0; all inputs v il -0.3 0.3 v 22 output high voltage: all inputs: i out = -4ma v oh 0.9 x v dd q- v output low voltage: all inputs: i out = 4ma v ol -0.2v input leakage current: any input 0v v in v dd (all other balls not under test = 0v) i i -1.0 1.0 a output leakage current: dqs are disabled; 0v v out v dd q i oz -1.5 1.5 a table 14: dc electrical characteristics and opera ting conditions (h version) notes: 1, 5, 6; note s appear on page 54; v dd = +1.8 0.1v, v dd q = +1.8v 0.1v parameter/condition symbol min max units notes supply voltage v dd 1.7 1.9 v i/o supply voltage v dd q1.7 1.9 v input high voltage: logic 1; all inputs v ih 0.8 x v dd qv dd q + 0.3 v 22 input low voltage: logic 0; all inputs v il -0.3 +0.3 v 22 output high voltage: all inputs: iout = -4ma v oh 0.9 x v dd q? v output low voltage: all inputs: iout = 4ma v ol ?0.2v input leakage current: any input 0v vin v dd (all other balls not under test = 0v) i i -1.0 1.0 a output leakage current: dqs are disabled; 0v vout v dd q i oz -1.5 1.5 a
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 48 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram electrical specifications table 15: electrical characteristics an d recommended ac operating conditions notes: 5, 6, 8, 9, 11; notes appear on page 54 ac characteristics -75 -8 -10 parameter symbol min max min max min max units notes access time from clk (pos. edge) cl = 3 t ac (3) 6 7 7 ns 9 cl = 2 t ac (2) 7 8 8 ns 9 cl = 1 t ac (1) - - 19 22 ns 9 address hold time t ah 1 1 1 ns address setup time t as 1.5 2.5 2.5 ns clk high-level width t ch 3 3 3 ns clk low-level width t cl 3 3 3 ns clock cycle time cl = 3 t ck (3) 7.5 8 100 10 100 ns 23 cl = 2 t ck (2) 9 9 100 12 100 ns 23, 31 cl = 1 t ck (1) - 20 100 25 100 ns cke hold time t ckh 1 1 1 ns cke setup time t cks 2.5 2.5 2.5 ns cs#, ras#, cas#, we#, dqm hold time t cmh 1 1 1 ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 2.5 2.5 ns data-in hold time t dh 1 1 1 ns data-in setup time t ds 1.5 2.5 2.5 ns data-out high-z time cl = 3 t hz (3) 6 7 7 ns 10 cl = 2 t hz (2) 7 8 8 ns 10 cl = 1 t hz (1) - 19 22 ns 10 data-out low-z time t lz 1 1 1 ns data-out hold time (load) t oh 2.5 2.5 2.5 ns data-out hold time (no load) t oh n 1.8 1.8 1.8 ns 27 active to precharge command t ras 44 120000 48 120000 50 120000 ns active to active command period t rc 67.5 72 90 ns active to read or write delay t rcd 19 20 20 ns refresh period (4,096 rows) t ref 64 64 64 ms auto refresh period t rfc 80 80 100 ns precharge command period t rp 19 19 20 ns active bank a to active bank b command t rrd 15 16 20 ns transition time t t 0.3 1.2 0.5 1.2 0.5 1.2 ns 7 write recovery time t wr (a) 1 clk + 7.5ns 1 clk +7ns 1 clk +5ns ?24 t wr (m) 15 15 15 ns 25 exit self refresh to active command t xsr 67 80 100 ns 20
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 49 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram electrical specifications table 16: ac function al characteristics notes: 5, 6, 7, 8, 9, 11; notes appear on page 54 parameter symbol -75 -8 -10 units notes read/write command to read/write command t ccd 1 1 1 t ck 17 cke to clock disable or power-down entry mode t cked 1 1 1 t ck 14 cke to clock enable or po wer-down exit setup mode t ped 1 1 1 t ck 14 dqm to input data delay t dqd 0 0 0 t ck 17 dqm to data mask during writes t dqm 0 0 0 t ck 17 dqm to data high-z during reads t dqz 2 2 2 t ck 17 write command to input data delay t dwd 0 0 0 t ck 17 data-in to active command t dal 5 5 5 t ck 15, 21 data-in to precharge command t dpl 2 2 2 t ck 16, 21 last data-in to burst stop command t bdl 1 1 1 t ck 17 last data-in to ne w read/write command t cdl 1 1 1 t ck 17 last data-in to precharge command t rdl 2 2 2 t ck 16, 21 load mode register command to active or refresh command t mrd 2 2 2 t ck 26 data-out to high-z from precharge command cl = 3 t roh(3) 3 3 3 t ck 17 cl = 2 t roh(2) 2 2 2 t ck 17 cl = 1 t roh(1) - 1 1 t ck 17 table 17: i dd specifications and co nditions (lc version) notes: 1, 5, 6, 11, 13; notes appear on page 54; v dd = +3.3v 0.3v, v dd q = +3.3v 0.3v max parameter/condition symbol -75 -8 -10 units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 170 170 145 ma 3, 18, 19, 28 standby current: power-down mode; all banks idle; cke = low i dd 2p 400 400 400 a 28 standby current: power-down mode; all banks idle; cke = high i dd 2n 30 30 30 ma 28 standby current: active mode ; cke = high; cs# = high; all banks active after t rcd met; no accesses in progress i dd 3n 40 40 40 ma 3, 12, 19, 28 standby current: active mode ; cke = low; cs# = high; all banks active; no accesses in progress i dd 3p 30 30 30 ma 3, 12, 19, 28 operating current: burst mode ; continuous burst; read or write; all banks active, ha lf dqs toggling every cycle i dd 4 125 125 100 ma 3, 18, 19, 28 auto refresh current cke = high; cs# = high t rfc = t rfc (min) i dd 5 255 255 205 ma 3, 12, 18, 19, 28, 29 t rfc = 15.625s i dd 6 2.5 2.5 2.5 ma deep power-down i zz 10 10 10 a
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 50 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram electrical specifications table 18: i dd specifications and co nditions (v version) notes: 1, 5, 6, 11, 13; notes appear on page 54; v dd = +2.5 0.2v, v dd q = +2.5 0.2v max parameter/condition symbol -75 -8 -10 units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 170 170 145 ma 3, 18, 19, 28 standby current: power-down mode; all banks idle; cke = low i dd 2p 400 400 400 a 28 standby current: power-down mode; all banks idle; cke = high i dd 2n 30 30 30 ma 28 standby current: active mode ; cke = high; cs# = high; all banks active after t rcd met; no accesses in progress i dd 3n 40 40 40 ma 3, 12, 19, 28 standby current: active mode ; cke = low; cs# = high; all banks active; no accesses in progress i dd 3p 30 30 30 ma 3, 12, 19, 28 operating current: burst mode; continuous burst; read or write; all banks active, ha lf dqs toggling every cycle i dd 4 125 125 100 ma 3, 18, 19, 28 auto refresh current cke = high; cs# = high t rfc = t rfc (min) i dd 5 255 255 200 ma 3, 12, 18, 19, 28, 29 t rfc = 15.625s i dd 6 2.5 2.5 2.5 ma deep power-down i zz 10 10 10 a table 19: i dd specifications and co nditions (h version) notes: 1, 5, 6, 11, 13; notes appear on page 54; v dd = 1.8 0.1v, v dd q = 1.8v 0.1v max parameter/condition symbol -75 -8 -10 units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 125 125 100 ma 3, 18, 19, 28 standby current: power-down mode; all banks idle; cke = low i dd 2p 300 300 300 a 28 standby current: power-down mode; all banks idle; cke = high i dd 2n 20 20 20 ma 28 standby current: active mode ; cke = high; cs# = high; all banks active after t rcd met; no accesses in progress i dd 3n 30 30 30 ma 3, 12, 19, 28 standby current: active mode ; cke = low; cs# = high; all banks active; no accesses in progress i dd 3p 20 20 20 ma 3, 12, 19, 28 operating current: burst mode; continuous burst; read or write; all banks active, ha lf dqs toggling every cycle i dd 4 85 85 65 ma 3, 18, 19, 28 auto refresh current cke = high; cs# = high t rfc = t rfc (min) i dd 5 210 210 170 ma 3, 12, 18, 19, 28, 29 t rfc = 15.625s i dd 62.5 2.5 2.5ma deep power-down i zz 10 10 10 a
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 51 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram electrical specifications figure 31: typical self refresh current vs. tempera ture ? 3.3v part table 20: i dd 7 ? self refresh current options notes: 4, 30; notes appear on page 54 and page 55 temperature compensated self refresh parameter/condition max temperature v dd = 3.3 v dd = 2.5 v dd = 1.8 units notes self refresh current: cke = low ? 4-bank refresh 85oc 800 800 600 a 4, 30 70oc 647 647 480 a 4, 30 45oc 503 503 370 a 4, 30 15oc 432 432 315 a 4, 30 self refresh current: cke = low ? 2-bank refresh 85oc 600 600 450 a 4, 30 70oc 513 513 380 a 4, 30 45oc 437 437 320 a 4, 30 15oc 398 398 290 a 4, 30 self refresh current: cke = low ? 1-bank refresh 85oc 500 500 375 a 4, 30 70oc 447 447 330 a 4, 30 45oc 403 403 295 a 4, 30 15oc 382 382 278 a 4, 30 self refresh current: cke = low ? half-bank refresh 85oc 450 450 338 a 4, 30 70oc 413 413 305 a 4, 30 45oc 387 387 283 a 4, 30 15oc 373 373 271 a 4, 30 self refresh current: cke = low ? quarter-bank refresh 85oc 425 425 319 a 4, 30 70oc 397 397 293 a 4, 30 45oc 378 378 276 a 4, 30 15oc 369 369 268 a 4, 30 0 50 100 150 200 250 300 350 400 450 500 550 600 -40-30-20-10 0 1020304050607080 temperature (c) currrent (a) idd7 ? 4-bank idd7 ? 2-bank idd7 ? 1-bank idd7 ? 1/2-bank idd7 ? 1/4-bank
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 52 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram electrical specifications figure 32: typical self refresh current vs. tempera ture ? 2.5v part figure 33: typical self refresh current vs. tempera ture ? 1.8v part 0 50 100 150 200 250 300 350 400 450 500 550 600 -40-30-20-10 0 1020304050607080 temperature (c) currrent (a) idd7 ? 4-bank idd7 ? 2-bank idd7 ? 1-bank idd7 ? 1/2-bank idd7 ? 1/4-bank 0 50 100 150 200 250 300 350 400 450 -40-30-20-10 0 1020304050607080 temperature (c) currrent (a) idd7 ? 4-bank idd7 ? 2-bank idd7 ? 1-bank idd7 ? 1/2-bank idd7 ? 1/4-bank
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 53 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram electrical specifications table 21: capacitance note: 2; notes appear on page 54 parameter symbol min max units notes input capacitance: clk c i1 2.5 4.5 pf 2 input capacitance: all other input-only balls c i2 2.5 4.5 pf 2 input/output capacitance: dqs c io 4.0 6.0 pf 2
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 54 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram notes notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd , v dd q = +1.8v, 2.5v or 3.3v; t a = 25c; ball under test biased at 0.9v, 1.25v, and 1.4 v respectively. f = 1 mhz. 3. i dd is dependent on output loading and cy cle rates. specified values are obtained with minimum cycle time and the outputs open. 4. enables on-chip refres h and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-40c t a +85c for t a on it parts) is ensured. 6. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v dd q must be pow- ered up simultaneously. v ss and v ss q must be at same potential.) the two auto refresh command wake-ups should be repeated any time the t ref refresh require- ment is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specification, the clock and cke must tran- sit between v ih and v il (or between v il and v ih ) in a monotonic manner. 9. outputs measured for 1.8v at 0.9v, 2.5v at 1.25v, or 3.3v at 1.65v with equivalent load: test loads with full dq driver strength. performance will vary with actual system dq bus capacitive loading, terminatio n, and programmed drive strength. 10. t hz defines the time at which the output achi eves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i dd tests have v il and v ih , with timing referenced to v ih /2 = crossover point. if the input transition time is longer than t t (max), then the timing is refer- enced at v il (max) and v ih (min) and no longer at the v ih /2 crossover point. 12. other input signals are allowed to transiti on no more than once every two clocks and are otherwise at valid v ih or v il levels. 13. i dd specifications are tested after th e device is properly initialized. 14. timing actually specified by t cks; clock(s) specified as a reference only at minimum cycle rate. 15. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 16. timing actually specified by t wr. 17. required clocks are specified by jedec functionality and are not dependent on any timing parameter. 18. the i dd current will increase or decrease pr oportionally according to the amount of frequency alteration for the test condition. 19. address transitions average on e transition every two clocks. q 20pf 1.8v option q 30pf 2.5/3.3v option
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 55 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram notes 20. clk must be toggled a minimum of two times during this period. 21. based on t ck = 7.5ns for -75, t ck = 8ns for -8, t ck = 10ns for -10, and cl = 3. 22. v ih overshoot: v ih (max) = v dd q + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 3ns. 23. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints sp ecified for the clock pin) du ring access or precharge states (read, write, including t wr, and precharge commands). cke may be used to reduce the data rate. 24. auto precharge mode only. the precharge timing budget ( t rp) begins at 7ns for -8 after the first clock delay, after the last wr ite is executed. may not exceed limit set for precharge mode. 25. precharge mode only. 26. jedec specifies three clocks. 27. parameter guaran teed by design. 28. for -10, cl = 3 and t ck = 10ns. 29. cke is high during refresh command period t rfc (min) else cke is low. the i dd 6 limit is actually a nominal value and does not result in a fail value. 30. values for i dd 7 for 85c are 100 percent tested. values for 70c, 45c, and 15c are sam- pled only. 31. t ck (2) min is 9.6 ns for -7.5 and -8 speed 1.8v product.
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 56 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram timing diagrams timing diagrams figure 34: initialize and load mode register 1,2 notes: 1. the two auto refresh commands at t9 an d t19 may be applied before either load mode register (lmr) command. 2. pre = precharge command, lmr = load mode register command, ar = auto refresh command, act = active command, ra = row address, ba = bank address. 3. optional re fresh command. 4. the load mode re gister for both mr/emr and 2 auto refresh commands can be in any order. however, all must occu r prior to an active command. 5. device timing is -10 with 100 mhz clock. see table 15, electrical characteristics an d recommended ac operating conditions, on page 48. c ke ba0, ba1 loa d exten d e d mo d e re g ister loa d mo d e re g ister t c k s power-up: v dd an d c lk sta b le t = 100s t c kh ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dqm 0-3 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq hi g h-z a0-a9, a11 ra a10 ra all bank s c lk t c k c ommand 5 lmr 4 nop pre 3 lmr 4 ar 4 ar 4 a c t 4 t c m s t c mh ba0 = l, ba1 = h t a s t ah t a s t ah ba0 = l, ba1 = l ( ) ( ) ( ) ( ) c ode c ode t a s t ah c ode c ode ( ) ( ) ( ) ( ) pre all bank s t a s t ah ( ) ( ) ( ) ( ) t0 t1 t3 t5 t7 t9 t19 t29 don ? t c are ba ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rp t mrd t mrd t rp t rf c t rf c ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 57 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram timing diagrams figure 35: power-down mode note: violating refresh requirements during power-down may result in a loss of data. see table 15, electrical characteristics an d recommended ac operating conditions, on page 48. t ch t cl t ck two clock cycles cke clk dq all banks idle, enter power-down mode precharge all active banks input buffers gated off while in power-down mode exit power-down mode ( ) ( ) ( ) ( ) don?t care t cks t cks command t cmh t cms precharge nop nop active nop ( ) ( ) ( ) ( ) all banks idle ba0, ba1 bank bank(s) ( ) ( ) ( ) ( ) high-z t ah t as t ckh t cks dqml, dqmu ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) a0-a9, a11 row ( ) ( ) ( ) ( ) all banks single bank a10 row ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 tn + 2
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 58 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram timing diagrams figure 36: clock suspend mode notes: 1. for this example, bl = 2, cl = 3, and auto precharge is disabled. 2. a9 and a11 = ?don?t care.? see table 15, electrical characteristics an d recommended ac operating conditions, on page 48. t ch t cl t ck t ac t lz dqm 0-3 clk dq a10 t oh d out m t ah t as t ah t as t ah t as bank t dh d out e t ac t hz d out m + 1 command t cmh t cms nop nop nop nop nop read write don?t care undefined cke t cks t ckh bank column m t ds d out e + 1 nop t ckh t cks t cmh t cms 2 column e 2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 ba0, ba1 a0-a9, a11
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 59 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram timing diagrams figure 37: auto refresh mode note: each auto refresh command performs a refresh cycle. ba ck-to-back commands are not required. see table 15, electrical characteristics an d recommended ac operating conditions, on page 48. undefined don?t care t ch t cl t ck cke clk dq t rfc ( ) ( ) ( ) ( ) ( ) ( ) t rp ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) command t cmh t cms nop nop ( ) ( ) ( ) ( ) bank active auto refresh ( ) ( ) ( ) ( ) nop nop precharge precharge all active banks auto refresh t rfc high-z bank(s) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t ah t as t ckh t cks ( ) ( ) nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) row ( ) ( ) ( ) ( ) all banks single bank a10 row ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 to + 1 ba0, ba1 a0-a9, a11 dqm 0-3
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 60 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram timing diagrams figure 38: self refresh mode note: each auto refresh command performs a refresh cycle. ba ck-to-back commands are not required. see table 15, electrical characteristics an d recommended ac operating conditions, on page 48. t ch t cl t ck t rp cke clk dq enter self refresh mode precharge all active banks t xsr clk stable prior to exiting self refresh mode exit self refresh mode (restart refresh time base) ( ) ( ) ( ) ( ) ( ) ( ) don?t care command t cmh t cms auto refresh precharge nop nop bank(s) high-z t cks ah as auto refresh > t ras t ckh t cks t t all banks single bank a10 t0 t1 t2 tn + 1 to + 1 to + 2 ba0, ba1 dqm 0-3 a0-a9, a11 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 61 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram timing diagrams figure 39: read ? w ithout auto precharge 1 notes: 1. for this example, bl = 4, cl = 2, and th e read burst is followed by a manual precharge. 2. a9 and a11 = ?don?t care.? see table 15, electrical characteristics an d recommended ac operating conditions, on page 48. all banks t ch t cl t ck t ac t lz t rp t ras t rcd cl t rc cke clk dq a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank(s) bank row row bank t hz t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms precharge nop nop nop active nop read nop active disable auto precharge single bank don?t care undefined t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 ba0, ba1 dqm 0-3 a0?a9, a11
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 62 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram timing diagrams figure 40: read ? with auto precharge 1 notes: 1. for this example, bl = 4, cl = 2. 2. a9 and a11 = ?don?t care.? see table 15, electrical characteristics an d recommended ac operating conditions, on page 48. t ch t cl t ck t ac t lz t rp t ras t rcd cl t rc cke clk dq a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank row row bank t hz t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms nop nop nop nop active nop read nop active enable auto precharge don?t care undefined t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 ba0, ba1 dqm 0-3 a0?a9, a11
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 63 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram timing diagrams figure 41: single read ? without auto precharge 1 notes: 1. for this example, bl = 4, cl = 2, and th e read burst is followed by a manual precharge. 2. a9 and a11 = ?don?t care.? 3. precharge comman d not allowed or t ras would be violated. see table 15, electrical characteristics an d recommended ac operating conditions, on page 48. all banks t ch t cl t ck t ac t lz t rp t ras t rcd cl t rc cke clk dq a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank(s) bank row row bank t hz command t cmh t cms nop nop 3 nop 3 precharge active nop read active nop disable auto precharge single bank don?t care undefined t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 ba0, ba1 dqm 0-3 a0?a9, a11
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 64 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram timing diagrams figure 42: single read ? with auto precharge 1 notes: 1. for this example, bl = 4, cl = 2, and th e read burst is followed by a manual precharge. 2. a9 and a11 = ?don?t care.? 3. precharge comman d not allowed or t ras would be violated. see table 15, electrical characteristics an d recommended ac operating conditions, on page 48. t ch t cl t ck t ac t rp t ras t rcd cl t rc cke clk dq a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank row row bank t hz command t cmh t cms nop nop nop 3 nop 3 read active nop active nop enable auto precharge don?t care undefined t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 ba0, ba1 dqm 0-3 a0?a9, a11
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 65 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram timing diagrams figure 43: alternatin g bank read accesses 1 notes: 1. for this example, bl = 4, cl = 2. 2. a9 and a11 = ?don?t care.? see table 15, electrical characteristics an d recommended ac operating conditions, on page 48. don?t care undefined enable auto precharge t ch t cl t ck t ac t lz clk dq a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row row row t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms nop nop active nop read nop active t oh d out b t ac t ac read enable auto precharge row active row bank 0 bank 0 bank 3 bank 3 bank 0 cke t ckh t cks column m 2 column b 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t rp - bank 0 t ras - bank 0 t rcd - bank 0 t rcd - bank 0 cl - bank 0 t rcd - bank 4 cl - bank 4 t t rc - bank 0 rrd ba0, ba1 dqm 0-3 a0?a9, a11
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 66 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram timing diagrams figure 44: read ? full-page burst 1 notes: 1. for this example, cl = 2. 2. a9 and a11 = ?don?t care.? 3. page left open; no t rp. see table 15, electrical characteristics an d recommended ac operating conditions, on page 48. t ch t cl t ck t ac t lz t rcd cas latency cke clk dq a10 t oh dout m t cmh t cms t ah t as t ah t as t ac t oh d out m +1 row row t hz t ac t oh d out m +1 t ac t oh d out m +2 t ac t oh d out m -1 t ac t oh d out m full-page burst does not self-terminate. can use burst terminate command. ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed 512 locations within same row don?t care undefined command t cmh t cms nop nop nop active nop read nop burst term nop nop ( ) ( ) ( ) ( ) nop ( ) ( ) ( ) ( ) t ah t as bank ( ) ( ) ( ) ( ) bank t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) column m 2 3 t0 t1 t2 t4 t3 t5 t6 tn + 1 tn + 2 tn + 3 tn + 4 ba0, ba1 dqm 0-3 a0-a9, a11
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 67 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram timing diagrams figure 45: read ? dqm operation 1 notes: 1. for this example, cl = 2. 2. a9 and a11 = ?don?t care.? see table 15, electrical characteristics an d recommended ac operating conditions, on page 48. t ch t cl t ck t ac t ac t lz t rcd cl cke clk dq a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row bank row bank t hz t ac t lz t oh d out m + 2 t oh d out m + 3 t hz command t cmh t cms nop nop nop nop active nop read nop nop disable auto precharge enable auto precharge don?t care undefined t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 ba0, ba1 dqm 0-3 a0?a9, a11
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 68 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram timing diagrams figure 46: write ? w ithout auto precharge 1 notes: 1. for this example, bl = 4, and the wr ite burst is followed by a manual precharge. 2. 15ns is required between and the precharge command, regardless of fre- quency. 3. a9 and a11 = ?don?t care.? see table 15, electrical characteristics an d recommended ac operating conditions, on page 48. disable auto precharge all banks t ch t cl t ck t rp t ras t rcd t rc cke clk dq a10 t cmh t cms t ah t as row bank bank row bank t wr 2 don?t care d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop nop active nop write precharge nop nop row bank row t ah t as t ah t as t dh t ds t dh t ds t dh t ds single bank t ckh t cks column m 3 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 dqm 0-3 ba0, ba1 a0?a9, a11 active
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 69 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram timing diagrams figure 47: write ? with auto precharge 1 notes: 1. for this example, bl = 4. 2. a9 and a11 = ?don?t care.? see table 15, electrical characteristics an d recommended ac operating conditions, on page 48. enable auto precharge t ch t cl t ck t rp t ras t rcd t rc cke clk dq a10 t cmh t cms t ah t as row bank row bank t wr 2 don?t care undefined d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop nop active nop write nop nop nop row bank row t ah t as t ah t as t dh t ds t dh t ds t dh t ds t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 dqm 0-3 ba0, ba1 a0?a9, a11 active
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 70 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram timing diagrams figure 48: single write ? without auto precharge 1 notes: 1. for this example, bl = 1, and the wr ite burst is followed by a manual precharge. 2. 15ns is required between and the precharge command, regardless of fre- quency. 3. a9 and a11 = ?don?t care.? 4. precharge command not allowed else t ras would be violated. see table 15, electrical characteristics an d recommended ac operating conditions, on page 48. all banks t ch t cl t ck t rp t ras t rcd t wr 2 t rc cke clk dq a10 t cmh t cms t ah t as t ah t as t ah t as row bank bank bank row row bank command t cmh t cms nop nop 4 nop 4 precharge active nop write active nop disable auto precharge single bank don?t care t ckh t cks column m 3 t0 t1 t2 t4 t3 t5 t6 t7 t8 ba0, ba1 dqm 0-3 a0?a9, a11 d in m t dh t ds
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 71 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram timing diagrams figure 49: single write ? with auto precharge 1 notes: 1. for this example, bl = 1, and the wr ite burst is followed by a manual precharge. 2. 15ns is required between and the precharge command, regardless of fre- quency. 3. a9 and a11 = ?don?t care.? 4. write command not allowed else t ras would be violated. see table 15, electrical characteristics an d recommended ac operating conditions, on page 48. t ch t cl t ck cke clk dq a10 t cmh t cms t ah t as t ah t as t ah t as row row bank bank row row bank command t cmh t cms nop nop nop 3 nop 3 write active nop 3 nop active nop enable auto precharge don?t care t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 ba0, ba1 dqm 0-3 a0?a9, a11 t rp t ras t rcd t rc t wr d in m t dh t ds
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 72 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram timing diagrams figure 50: alternating bank write accesses 1 notes: 1. for this example, bl = 4. 2. a9 and a11 = ?don?t care.? see table 15, electrical characteristics an d recommended ac operating conditions, on page 48. don?t care enable auto precharge t ch t cl t ck clk dq a10 t cmh t cms t ah t as t ah t as t ah t as row row row row command t cmh t cms nop nop active nop write nop nop active write enable auto precharge row active row bank 0 bank 0 bank 1 bank 1 bank 0 cke t ckh t cks column m 2 column b 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 t rp - bank 0 t ras - bank 0 t rcd - bank 0 t rcd - bank 0 t wr - bank 1 t wr - bank 0 t rcd - bank 1 t t rc - bank 0 rrd ba0, ba1 dqm 0-3 a0?a9, a11 d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 t dh t ds t dh t ds t dh t ds d in b t dh t ds d in b + 1 t dh t ds d in b + 2 t dh t ds d in m + 3 t dh t ds
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 73 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram timing diagrams figure 51: write ? full-page burst 1 notes: 1. a9 and a11 = ?don?t care.? 2. t wr must be satisfied pr ior to precharge command. 3. page left open; no t rp. see table 15, electrical characteristics an d recommended ac operating conditions, on page 48. t ch t cl t ck t rcd cke clk a10 t cms t ah t as t ah t as row row full-page burst does not self-terminate. can use burst terminate command to stop. 2, 3 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed don?t care command t cmh t cms nop nop nop active nop write burst term nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 t dh t ds t dh t ds t dh t ds d in m - 1 t dh t ds t ah t as bank ( ) ( ) ( ) ( ) bank t cmh t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 512 locations within same row column m 1 t0 t1 t2 t3 t4 t5 tn + 1 tn + 2 tn + 3 ba0, ba1 dqm 0-3 a0-a9, a11
pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 74 ?2003 micron technology, inc. all rights reserved. 256mb: x32 mobile sdram timing diagrams figure 52: write ? dqm operation 1 notes: 1. for this example, bl = 4. 2. a9 and a11 = ?don?t care.? see table 15, electrical characteristics an d recommended ac operating conditions, on page 48. don?t care t ch t cl t ck t rcd cke clk dq a10 t cms t ah t as row bank row bank enable auto precharge d in m + 3 t dh t ds d in m d in m + 2 t cmh command nop nop nop active nop write nop nop t cms t cmh t dh t ds t dh t ds t ah t as t ah t as disable auto precharge t ckh t cks column m 2 t0 t1 t2 t3 t4 t5 t6 t7 ba0, ba1 dqm 0-3 a0?a9, a11
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com cu stomer comment line: 800-932-4992 micron, the m logo, and the micron logo are tr ademarks of micron technology, inc. all other trademarks are the propert y of their respective owners. this data sheet contains minimum and maximum limits specified ov er the complete power supply and temperature range for production devices. although consid ered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 256mb: x32 mobile sdram package dimensions pdf: 09005aef80d460f2/source: 09005aef80cd8d41 micron technology, inc., reserves the right to change products or specifications without notice. 256mb sdram x32_2.fm - rev. g 6/05 75 ?2003 micron technology, inc. all rights reserved. package dimensions figure 53: 90-ball vfbga (8mm x 13mm) note: all dimensions are in millimeters. ball a1 id 1.00 max mold compound: epoxy novolac substrate material: plastic laminate solder ball material: 62% sn, 36% pb, 2% ag or 96.5% sn, 3%ag, 0.5% cu solder mask defined ball pads: ?0.40 13.00 0.10 ball a1 ball a9 ball a1 id 0.80 typ 0.80 typ 6.50 0.05 8.00 0.10 4.00 0.05 3.20 0.05 5.60 0.05 0.65 0.05 seating plane c 11.20 0.10 6.40 0.10 c 90x ?0.45 0.05 solder ball diameter refers to post reflow condition. the pre- reflow diameter is ?0.42 c l c l

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